Invalid register operand when updating
Instruction pipelining generally involves splitting a data processor into a series of stages called a pipeline.
11, 2002, which is incorporated herein in its enitrety by reference.
wherein the address of the wide operand in the memory is aligned to result in a plurality of low order bits of the address to not be required for retrieval of the wide operand, and those low order bits provide the indicia of the size of the wide operand.13. The size of the result for additional instructions may not be so constrained, and so utilize dedicated storage to which the result operand is placed on execution of the instruction.
In a processor including a functional unit coupled to a first data path having a first bit width, a second data path having a second bit width greater than the first bit width, a plurality of third data paths having a combined bit width less than the second bit width, a wide operand storage storing a wide operand, a register file including registers having the first bit width, the register file being connected to the third data paths, a method comprising: further comprising a step of rounding the result elements by one of a plurality of rounding operations including round-to-nearest, round-to-zero, round-to-negative infinity, and round-to-positive infinity. The dedicated storage may be implemented in a local memory tightly coupled to the logic circuits that comprise the functional unit.
In the present invention, source and result operands are provided which are substantially larger than the data path width of the processor.
There is also a need for a processor system capable of efficient handling of operands and results of greater overall size than the entire general register file. In addition, several classes of instructions will be provided which cannot be performed efficiently if the source operands or the at least one result operand are limited to the width and accessible number of general purpose registers.
Preferably, the processor using the technique has the ability to execute branches of instructions speculatively, and to recover if it is determined that the processor executed down an incorrect instruction branch. Accordingly, a write-after-read (WAR) dependency (or data hazard) exists between instructions (1) and (2).
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. This is achieved, in part, by using a general purpose register to specify at least one memory address from which at least more than one, but typically several data path widths of data can be read.
The present invention provides operands which are... To permit such a wide operand to be performed in a single cycle, a data path functional unit is augmented with dedicated storage to which the memory operand is copied on an initial execution of the instruction.
Fourth, the apparatus provides a means for handling precise recovery of interrupts when processing instructions in out-of-order sequence.1. The four reservation read ports are sourced to the execution units from the central pool of reservation station buffers 19, and the execution units direct the computed results to the completion buffer 18 entry pointed to by the destination tag assigned by the rename unit 12.
A method of performing register renaming and rapid pipeline recovery in a pipelined microprocessor capable of issuing and executing instructions out-of-order in a single processor cycle comprising the steps of; The subject matter of this application is related to that of patent application Ser. As reservation station buffers 19 and completion buffer 18 entries are assigned in pairs during the dispatch stage by the rename unit 12, they share the same tag.